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1 april 2006 dsc-2689/13 ?2006 integrated device technology, inc. i/o control address decoder memory array arbitration and interrupt logic address decoder i/o control r/ w l ce l oe l busy l a 9l a 0l 2689 drw 01 i/o 0l - i/o 7l ce l oe l r/ w l int l busy r i/o 0r -i/o 7r a 9r a 0r int r ce r oe r (2) (1,2) (1,2) (2) r/ w r ce r oe r 10 10 r/ w r , high speed 1k x 8 dual-port static sram idt7130sa/la idt7140sa/la features high-speed access ? commercial: 20/25/35/55/100ns (max.) ? industrial: 25/55/100ns (max.) ? military: 25/35/55/100ns (max.) low-power operation ? idt7130/idt7140sa ? active: 550mw (typ.) ? standby: 5mw (typ.) ? idt7130/idt7140la ? active: 550mw (typ.) ? standby: 1mw (typ.) master idt7130 easily expands data bus width to 16-or- more-bits using slave idt7140 functional block diagram notes: 1. idt7130 (master): busy is open drain output and requires pullup resistor. idt7140 (slave): busy is input. 2. open drain output: requires pullup resistor. on-chip port arbitration logic (idt7130 only) busy output flag on idt7130; busy input on idt7140 int flag for port-to-port communication fully asynchronous operation from either port battery backup operation?2v data retention (la only) ttl-compatible, single 5v 10% power supply military product compliant to mil-prf-38535 qml industrial temperature range (?40c to +85c) is available for selected speeds available in 48-pin dip, lcc and ceramic flatpack, 52-pin plcc, and 64-pin stqfp and tqfp green parts available, see ordering information
idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges 2 description the idt7130/idt7140 are high-speed 1k x 8 dual-port static rams. the idt7130 is designed to be used as a stand-alone 8-bit dual-port ram or as a "master" dual-port ram together with the idt7140 "slave" dual-port in 16-bit-or-more word width systems. using the idt master/slave dual-port ram approach in 16-or- more-bit memory system applications results in full-speed, error- free operation without the need for additional discrete logic. both devices provide two independent ports with separate con- trol, address, and i/o pins that permit independent asynchronous access for reads or writes to any location in memory. an automatic power down feature, controlled by ce , permits the on chip circuitry of each port to enter a very low standby power mode. fabricated using idt's cmos high-performance tech-nology, these devices typically operate on only 550mw of power. low- power (la) versions offer battery backup data retention capability, with each dual-port typically consuming 200w from a 2v battery. the idt7130/idt7140 devices are packaged in 48-pin sidebraze or plastic dips, lccs, flatpacks, 52-pin plcc, and 64-pin tqfp and stqfp. military grade products are manufactured in compli- ance with the latest revision of mil-prf-38535 qml, making it ideally suited to military temperature applications demanding the highest level of performance and reliability. pin configurations (1,2,3) notes: 1. all v cc pins must be connected to power supply. 2. all gnd pins must be connected to ground supply. 3. p48-1 package body is approximately .55 in x .61 in x .19 in. c48-2 package body is approximately .62 in x 2.43 in x .15 in. l48-1 package body is approximately .57 in x .57 in x .68 in. f48-1 package body is approximately .75 in x .75 in x .11 in. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking. 24 23 22 21 20 19 18 17 16 15 14 13 12 11 10 9 8 7 6 5 4 3 2 148 47 46 45 44 43 42 41 40 39 38 37 36 35 34 33 32 31 30 29 28 27 26 25 idt7130/40 porc p48-1 (4) & c48-2 (4) 48-pin dip top view (5) 2689 drw 02 gnd i/o 6r i/o 5r i/o 4r i/o 3r i/o 2r i/o 1r i/o 0r i/o 7l i/o 6l i/o 5l i/o 4l ce r ce l oe l a 0l int l busy l r/ w l r/ w r busy r int r v cc oe r a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r i/o 7r i/o 3l a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l , 01 / 08 / 02 i n 01 /
3 idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges index idt7130/40tf or pf pp64-1 & pn64-1 (4) 64-pin stqfp 64-pin tqfp top view (5) 8 9 10 11 12 13 14 15 16 1 2 3 4 5 6 7 46 45 44 43 42 41 40 39 38 37 36 35 34 47 48 33 i/o 6r n/c a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r i/o 7r oe r n/c n/c i/o 2l a 0l oe l a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l n/c n/c 2689 drw 05 1 7 1 8 1 9 2 0 3 2 3 1 3 0 2 9 2 8 2 7 2 6 2 5 2 4 2 3 2 2 2 1 4 9 5 0 5 1 5 2 6 3 6 2 6 1 6 0 5 9 5 8 5 7 5 6 5 5 5 4 5 3 6 4 n / c n / c n / c n / c n / c n / c g n d n / c n / c g n d n / c r / w r c e r v c c v c c b u s y l i n t l i / o 3 l i / o 4 l i / o 5 l i / o 6 l i / o 7 l i / o 0 r i / o 1 r i / o 2 r i / o 3 r i / o 4 r i / o 5 r r / w l c e l b u s y r i n t r , 01/08/02 idt7130/40j j52-1 (4) 52-pin plcc top view (5) index n / c g n d n / c n / c c e r c e l o e l a 0 l oe r a 0r a 1r a 2r a 3r a 4r a 5r a 6r a 7r a 8r a 9r n/c i/o 7r 46 45 44 43 42 41 40 39 38 37 36 35 34 i/o 3l a 1l a 2l a 3l a 4l a 5l a 6l a 7l a 8l a 9l i/o 0l i/o 1l i/o 2l 8 9 10 11 12 13 14 15 16 17 18 19 20 47 48 49 50 51 52 1 2 3 4 5 6 7 33 32 31 30 29 28 27 26 25 24 23 22 21 2689 drw 04 i n t l b u s y l r / w l r / w r b u s y r i n t r i / o 6 r v c c i / o 5 r i / o 4 r i / o 3 r i / o 2 r i / o 1 r i / o 0 r i / o 7 l i / o 6 l i / o 5 l i / o 4 l , 01/08/02 pin configurations (1,2,3) (con't.) notes: 1. all v cc pins must be connected to power supply. 2. all gnd pins must be connected to ground supply. 3. j52-1 package body is approximately .75 in x .75 in x .17 in. pp64-1 package body is approximately 10 mm x 10 mm x 1.4mm. pn64-1 package body is approximately 14mm x 14mm x 1.4mm. 4. this package code is used to reference the package diagram. 5. this text does not indicate orientation of the actual part-marking.
idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges 4 absolute maximum ratings (1) recommended dc operating conditions recommended operating temperature and supply voltage (1) dc electrical characteristics over the operating temperature and supply voltage range (v cc = 5.0v 10%) notes: 1. this parameter is determined by device characterization but is not production tested. 2. 3dv references the interpolated capacitance when the input and output signals switch from 0v to 3v or from 3v to 0v. capacitance (t a = +25c, f = 1.0mhz) stqfp and tqfp packages only note: 1. at vcc < 2.0v leakages are undefined. notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of the specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed vcc + 10% for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > vcc + 10%. notes: 1. v il (min.) > -1.5v for pulse width less than 10ns. 2. v term must not exceed vcc + 10%. notes: 1. this is the parameter t a . this is the "instant on" case temperature. symbol rating commercial & industrial military unit v te rm (2) terminal voltage with respect to gnd -0.5 to +7.0 -0.5 to +7.0 v t bias temperature under bias -55 to +125 -65 to +135 o c t stg storage temperature -65 to +150 -65 to +150 o c i out dc output current 50 50 ma 26 89 tbl 01 symbol parameter min. typ. max. unit v cc supply voltage 4.5 5.0 5.5 v gnd ground 0 0 0 v v ih input high voltage 2.2 ____ 6.0 (2 ) v v il input low voltage -0.5 (1) ____ 0.8 v 2689 tbl 02 grade ambient temperature gnd vcc military -55 o c to +125 o c0v 5.0v + 10% commercial 0 o c to +70 o c0v 5.0v + 10% industrial -40 o c to +85 o c0v 5.0v + 10% 2689 tbl 03 symbol parameter (1) conditions max. unit c in input capacitance v in = 3dv 9 pf c out output capacitance v out = 3dv 10 pf 2689 tbl 05 symbol parameter test conditions 7130sa 7140sa 7130la 7140la unit min. max. min. max. |i li | input leakage current (1) v cc = 5.5v, v in = 0v to v cc ___ 10 ___ 5a |i lo | output leakage current (1 ) v cc - 5.5v, ce = v ih , v out = 0v to v cc ___ 10 ___ 5a v ol output low voltage (i/o 0 -i/o 7 )i ol = 4ma ___ 0.4 ___ 0.4 v v ol open drain output low voltage ( busy , int ) i ol = 16ma ___ 0.5 ___ 0.5 v v oh output high voltage i oh = -4ma 2.4 ___ 2.4 ___ v 2689 tbl 04
5 idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges dc electrical characteristics over the operating temperature and supply voltage range (1,5) (v cc = 5.0v 10%) notes: 1. 'x' in part numbers indicates power rating (sa or la). 2. plcc , tqfp and stqfp packages only. 3. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency read cycle of 1/t cyc , and using ?ac test conditions? of input levels of gnd to 3v. 4. f = 0 means no address or control lines change. applies only to inputs at cmos level standby. 5. vcc = 5v, t a =+25c for typ and is not production tested. vcc dc = 100 ma (typ) 6. port "a" may be either left or right port. port "b" is opposite from port "a". 7130x20 (2 ) 7140x20 (2 ) com'l only 7130x25 7140x25 com'l, ind & military 7130x35 7140x35 com'l & military symbol parameter test condition version typ. max. typ. max. typ. max. unit i cc dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled f = f max (3 ) com'l sa la 110 110 250 200 110 110 220 170 110 110 165 120 ma mil & ind sa la ____ ____ ____ ____ 110 110 280 220 110 110 230 170 i sb1 standby current (both ports - ttl level inputs) ce l and ce r = v ih f = f max (3 ) com'l sa la 30 30 65 45 30 30 65 45 25 25 65 45 ma mil & ind sa la ____ ____ ____ ____ 30 30 80 60 25 25 80 60 i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (6) active port outputsdisabled, f= f max (3 ) com'l sa la 65 65 165 125 65 65 150 115 50 50 125 90 ma mil & ind sa la ____ ____ ____ ____ 65 65 160 125 50 50 150 115 i sb3 full standby current (both ports - cmos level inputs) ce l and ce r > v cc - 0.2v, v in > v cc - 0.2v or v in < 0.2v, f = 0 (4) com'l sa la 1.0 0.2 15 5 1.0 0.2 15 5 1.0 0.2 30 10 ma mil & ind sa la ____ ____ ____ ____ 1.0 0.2 30 10 ____ ____ ____ ____ i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v cc - 0.2v (6 ) v in > v cc - 0.2v or v in < 0.2v active port outputs disabled, f = f max (3) com'l sa la 60 60 155 115 60 60 145 105 45 45 110 85 ma mil & ind sa la ____ ____ ____ ____ 60 60 155 115 45 45 145 105 2689 tbl 06a 7130x55 7140x55 com'l, ind & military 7130x100 7140x100 com'l, ind & military symbol parameter test condition version typ. max. typ. max. unit i cc dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled f = f max (3 ) com'l sa la 110 110 155 110 110 110 155 110 ma mil & ind sa la 110 110 190 140 110 110 190 140 i sb1 standby current (both ports - ttl level inputs) ce l and ce r = v ih f = f max (3 ) com'l sa la 20 20 65 35 20 20 55 35 ma mil & ind sa la 20 20 65 45 20 20 65 45 i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (6) active port outputs disabled, f= f max (3 ) com'l sa la 40 40 110 75 40 40 110 75 ma mil & ind sa la 40 40 125 90 40 40 125 90 i sb3 full standby current (both ports - cmos level inputs) ce l and ce r > v cc - 0.2v, v in > v cc - 0.2v or v in < 0.2v, f = 0 (4) com'l sa la 1.0 0.2 15 4 1.0 0.2 15 4 ma mil & ind sa la 1.0 0.2 30 10 1.0 0.2 30 10 i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v cc - 0.2v (6 ) v in > v cc - 0.2v or v in < 0.2v active port outputs disabled, f = f max (3) com'l sa la 40 40 100 70 40 40 95 70 ma mil & ind sa la 40 40 110 85 40 40 110 80 2689 tbl 06b
idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges 6 data retention waveform v cc ce 4.5v 4.5v data retention mode t cdr t r v ih v ih v dr v dr 2.0v 2692 drw 06 , data retention characteristics (la version only) notes: 1. v cc = 2v, t a = +25c, and is not production tested. 2. t rc = read cycle time 3. this parameter is guaranteed but not production tested. 7130la/7140la symbol parameter test condition min. typ. (1) max. unit v dr v cc for data re te ntion 2.0 ___ ___ v i ccdr data re te ntion current v cc = 2.0v, ce > v cc -0.2v mil. & ind. ___ 100 4000 a com'l. ___ 100 1500 t cdr (3 ) chip de select to data retentio n time v in > v cc -0.2v or v in < 0.2v 0 ___ ___ ns t r (3 ) operation recovery time t rc (2) ___ ___ ns 2689 tbl 07
7 idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges 5v 1250 ? *100pf for 55 and 100ns versions 30pf* 775 ? data out 5v 1250 ? 775 ? 5pf* data out 2689 drw 07 5v 270 ? 30pf* busy or int *100pf for 55 and 100ns versions ac test conditions figure 3. busy and int ac output test load figure 1. output test load figure 2. output test load (for t hz , t lz , t wz , and t ow ) * including scope and jig input pulse levels input rise/fall times input timing reference levels output reference levels output load gnd to 3.0v 5ns 1.5v 1.5v figures 1,2 and 3 2689 tbl 08
idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges 8 ac electrical characteristics over the operating temperature supply voltage range (3) notes: 1. transition is measured 0mv from low or high-impedance voltage output test load (figure 2). 2. plcc, tqfp and stqfp packages only. 3. 'x' in part numbers indicates power rating (sa or la). 4. this parameter is guaranteed by device characterization, but is not production tested. . 7130x20 (2 ) 7140x20 (2 ) com'l only 7130x25 7140x25 com'l, ind & military 7130x35 7140x35 com'l & military unit symbol parameter min.max.min.max.min.max. read cycle t rc read cycle time 20 ____ 25 ____ 35 ____ ns t aa address access time ____ 20 ____ 25 ____ 35 ns t ace chip enable access time ____ 20 ____ 25 ____ 35 ns t aoe output enable access time ____ 11 ____ 12 ____ 20 ns t oh output hold from address change 3 ____ 3 ____ 3 ____ ns t lz output low-z time (1,4) 0 ____ 0 ____ 0 ____ ns t hz output high-z time (1,4) ____ 10 ____ 10 ____ 15 ns t pu chip enable to power up time (4) 0 ____ 0 ____ 0 ____ ns t pd chip disable to power down time (4 ) ____ 20 ____ 25 ____ 35 ns 2689 tb l 09a 7130x55 7140x55 com'l, ind & military 7130x100 7140x100 com'l, ind & military unit symbol parameter min. max. min. max. read cycle t rc re ad cycle time 55 ____ 100 ____ ns t aa address access time ____ 55 ____ 100 ns t ace chip enable access time ____ 55 ____ 100 ns t aoe output enable access time ____ 25 ____ 40 ns t oh output hold from address change 3 ____ 10 ____ ns t lz output low-z time (1,4) 5 ____ 5 ____ ns t hz output high-z time (1,4) ____ 25 ____ 40 ns t pu chip enable to power up time (4 ) 0 ____ 0 ____ ns t pd chip disable to power down time (4) ____ 50 ____ 50 ns 2689 tbl 09b
9 idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges timing waveform of read cycle no. 2, either side (3) notes: 1. timing depends on which signal is asserted last, oe or ce . 2. timing depends on which signal is deaserted first, oe or ce . 3. r/ w = v ih and oe = v il , and the address is valid prior to or coincidental with ce transition low. 4. start of valid data depends on which timing becomes effective last t aoe , t ace , t aa , and t bdd . timing waveform of read cycle no. 1, either side (1) address data out t rc t oh previous data valid t aa t oh data valid 2689 drw 08 t bddh (2,3) busy out notes: 1. r/ w = v ih , ce = v il , and is oe = v il . address is valid prior to the coincidental with ce transition low. 2. t bdd delay is required only in the case where the opposite port is completing a write operation to the same the address location. f or simultaneous read operations, busy has no relationship to valid output data. 3. start of valid data depends on which timing becomes effective last t aoe , t ace , t aa , and t bdd . ce t ace t aoe t hz t lz t pd valid data t pu 50% oe data out current i cc i ss 50% 2689 drw 09 (4) (1) (1) (2) (2) (4) t lz t hz
idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges 10 ac electrical characteristics over the operating temperature supply voltage range (5) notes: 1. transition is measured 0mv from low or high-impedance voltage with output test load (figure 2). this parameter is guaranteed by device characterization but is not production tested. 2. plcc, tqfp and stqfp packages only. 3. for master/slave combination, t wc = t baa + t wp , since r/ w = v il must occur after t baa. 4. if oe is low during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off data to be placed on the bus for the required t dw . if oe is high during a r/w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . 5. 'x' in part numbers indicates power rating (sa or la). symbol parameter 7130x20 (2 ) 7140x20 (2 ) com'l only 7130x25 7140x25 com'l, ind & military 7130x35 7140x35 com'l & military unit min. max. min. max. min. max. wri t e cycl e t wc write cycle time (3) 20 ____ 25 ____ 35 ____ ns t ew chip enable to end-of-write 15 ____ 20 ____ 30 ____ ns t aw address valid to end-of-write 15 ____ 20 ____ 30 ____ ns t as address set-up time 0 ____ 0 ____ 0 ____ ns t wp write pulse width (4) 15 ____ 15 ____ 25 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t dw data valid to end-of-write 10 ____ 12 ____ 15 ____ ns t hz output high-z time (1) ____ 10 ____ 10 ____ 15 ns t dh data ho ld time 0 ____ 0 ____ 0 ____ ns t wz write enable to output in high-z (1 ) ____ 10 ____ 10 ____ 15 ns t ow outp ut active fro m end-of-write (1 ) 0 ____ 0 ____ 0 ____ ns 2689 tbl 10a symbol parameter 7130x55 7140x55 com'l, ind & military 7130x100 7140x100 com'l, ind & military unit min. max. min. max. wri t e cycl e t wc write cycle time (3) 55 ____ 100 ____ ns t ew chip enable to end-of-write 40 ____ 90 ____ ns t aw address valid to end-of-write 40 ____ 90 ____ ns t as address set-up time 0 ____ 0 ____ ns t wp write pulse width (4) 30 ____ 55 ____ ns t wr write recovery time 0 ____ 0 ____ ns t dw data valid to end-of-write 20 ____ 40 ____ ns t hz output high-z time (1) ____ 25 ____ 40 ns t dh data ho ld time 0 ____ 0 ____ ns t wz write enable to output in high-z (1 ) ____ 25 ____ 40 ns t ow outp ut active fro m end-of-write (1 ) 0 ____ 0 ____ ns 2689 tbl 10b
11 idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges timing waveform of write cycle no. 2, ( ce controlled timing) (1,5) notes: 1. r/ w or ce must be high during all address transitions. 2. a write occurs during the overlap (t ew or t wp ) of ce = v il and r/ w = v il. 3. t wr is measured from the earlier of ce or r/ w going high to the end of the write cycle. 4. during this period, the l/o pins are in the output state and input signals must not be applied. 5. if the ce low transition occurs simultaneously with or after the r/ w low transition, the outputs remain in the high impedance state. 6. timing depends on which enable signal ( ce or r/ w ) is asserted last. 7. this parameter is determined be device characterization, but is not production tested. transition is measured 0mv from stead y state with the output test load (figure 2). 8. if oe is low during a r/ w controlled write cycle, the write pulse width must be the larger of t wp or (t wz + t dw ) to allow the i/o drivers to turn off data to be placed on the bus for the required t dw . if oe is high during a r/ w controlled write cycle, this requirement does not apply and the write pulse can be as short as the specified t wp . timing waveform of write cycle no. 1, (r/ w controlled timing) (1,5,8) t wc address oe ce r/ w data out data in t as (6) t ow t dw t dh t aw t wp (2) t hz (7) (4) (4) t wz (7) t hz (7) 2689 drw 10 t wr (3) t wc address ce r/ w data in t as (6) t ew (2) t wr (3) t dw t dh t aw 2689 drw 11
idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges 12 ac electrical characteristics over the operating temperature and supply voltage range (7) notes: 1. plcc, tqfp and stqfp packages only. 2. port-to-port delay through ram cells from the writing port to the reading port, refer to ?timing waveform of write with port -to-port read and busy ." 3. to ensure that the earlier of the two ports wins. 4. t bdd is a calculated parameter and is the greater of 0, t wdd ? t wp (actual) or t ddd ? t dw (actual). 5. to ensure that a write cycle is inhibited on port 'b' during contention on port 'a'. 6. to ensure that a write cycle is completed on port 'b' after contention on port 'a'. 7. 'x' in part numbers indicates power rating (s or l). 7130x20 (1 ) 7140x20 (1 ) com'l only 7130x25 7140x25 com'l, ind & military 7130x35 7140x35 com'l & military symbol parameter min.max.min.max.min.max.unit busy timing (for master idt 7130) t baa busy access time from address ____ 20 ____ 20 ____ 20 ns t bda busy disable time from address ____ 20 ____ 20 ____ 20 ns t ba c busy access time from chip enable ____ 20 ____ 20 ____ 20 ns t bdc busy disable time from chip enable ____ 20 ____ 20 ____ 20 ns t wh write hold after busy (6) 12 ____ 15 ____ 20 ____ ns t wdd write pulse to data delay (2 ) ____ 40 ____ 50 ____ 60 ns t dd d write data vali d to read data de lay (2) ____ 30 ____ 35 ____ 35 ns t ap s arbitration priority set-up time (3 ) 5 ____ 5 ____ 5 ____ ns t bdd busy disable to valid data (4 ) ____ 25 ____ 35 ____ 35 ns busy input timing (for slave idt 7140) t wb write to busy input (5 ) 0 ____ 0 ____ 0 ____ ns t wh write hold after busy (6) 12 ____ 15 ____ 20 ____ ns t wdd write pulse to data delay (2 ) ____ 40 ____ 50 ____ 60 ns t dd d write data vali d to read data de lay (2) ____ 30 ____ 35 ____ 35 ns 26 89 tb l 11 a 7130x55 7140x55 com'l, ind & military 7130x100 7140x100 com'l, ind & military symbol parameter min. max. min. max. unit busy timing (for master idt 7130) t baa busy access time from address] ____ 30 ____ 50 ns t bda busy disable time from address ____ 30 ____ 50 ns t ba c busy access time from chip enable ____ 30 ____ 50 ns t bdc busy disable time from chip enable ____ 30 ____ 50 ns t wh write hold after busy (6) 20 ____ 20 ____ ns t wdd write pulse to data delay (2 ) ____ 80 ____ 120 ns t dd d write data valid to read data delay (2 ) ____ 55 ____ 100 ns t ap s arbitration priority set-up time (3 ) 5 ____ 5 ____ ns t bdd busy disable to valid data (4 ) ____ 55 ____ 65 ns busy input timing (for slave idt 7140) t wb write to busy input (5) 0 ____ 0 ____ ns t wh write hold after busy (6) 20 ____ 20 ____ ns t wdd write pulse to data delay (2 ) ____ 80 ____ 120 ns t dd d write data valid to read data delay (2 ) ____ 55 ____ 100 ns 2689 tbl 11b
13 idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges timing waveform of write with port-to-port read and busy (2,3,4) notes: 1. to ensure that the earlier of the two ports wins. t bdd is ignored for slave (idt7140). 2. ce l = ce r = v il 3. oe = v il for the reading port. 4. all timing is the same for the left and right ports. port 'a' may be either the left or right port. port "b" is opposite from port "a". timing waveform of write with busy (3) notes: 1. t wh must be met for both busy input (idt7140, slave) or output (idt7130 master). 2. busy is asserted on port "b" blocking r/ w "b" , until busy "b" goes high. 3. all timing is the same for the left and right ports. port "a" may be either the left or right port. port "b" is oppsite from port "a". busy "b" 2689 drw 13 r/ w "a" t wp t wh t wb r/ w "b" (2) (1) , t wc t wp t dw t dh t bdd t ddd t bda t wdd addr "b" data out"b" data in"a" addr "a" match valid match valid r/ w "a" busy "b" t aps (1) 2689 drw 12 t baa
idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges 14 ac electrical characteristics over the operating temperature and supply voltage range (2) notes: 1. plcc, tqfp and stqfp package only. 2. 'x' in part numbers indicates power rating (sa or la). timing waveform of busy arbitration controlled by ce timing (1) timing waveform by busy arbitration controlled by address match timing (1) t aps addr 'a' and 'b' addresses match t bac t bdc ce 'b' ce 'a' busy 'a' 2689 drw 14 (2) busy 'b' addresses do not match addresses match t aps addr 'a' addr 'b' 2689 drw 15 (2) t baa t bda t rc or t wc notes: 1. all timing is the same for left and right ports. port ?a? may be either left or right port. port ?b? is the opposite from por t ?a?. 2. if t aps is not satisified, the busy will be asserted on one side or the other, but there is no guarantee on which side busy will be asserted (7130 only). 7130x20 (1) 7140x20 (1) com'l only 7130x25 7140x25 com'l, ind & military 7130x35 7140x35 com'l & military symbol parameter min. max. min. max. min. max. unit interrupt timing t as address set-up time 0 ____ 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ 0 ____ ns t ins interrupt set time ____ 20 ____ 25 ____ 25 ns t inr interrupt rese t time ____ 20 ____ 25 ____ 25 ns 2689 tbl 12a
15 idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges t ins addr 'a' int 'b' interrupt address t wc t as r/ w 'a' t wr 2689 drw 16 (3) (3) (2) (4) int set: timing waveform of interrupt mode (1) notes: . 1. all timing is the same for left and right ports. port ?a? may be either left or right port. port ?b? is the opposite from po rt ?a?. 2. see interrupt truth table ii. 3. timing depends on which enable signal ( ce or r/ w ) is asserted last. 4. timing depends on which enable signal ( ce or r/ w ) is de-asserted first. int clear: ac electrical characteristics over the operating temperature and supply voltage range (1) notes: 1. 'x' in part numbers indicates power rating (sa or la). 7130x55 7140x55 com'l, ind & military 7130x100 7140x100 com'l, ind & military symbol parameter min. max. min. max. unit interrupt timing t as address set-up time 0 ____ 0 ____ ns t wr write recovery time 0 ____ 0 ____ ns t ins interrupt set time ____ 45 ____ 60 ns t inr inte rrup t rese t time ____ 45 ____ 60 ns 2689 tbl 12b t rc interrupt clear address addr 'b' oe 'b' t inr int 'a' 2689 drw 17 t as (3) (3)
idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges 16 truth table i ? non-contention read/write control (4) truth tables truth table ii ? interrupt flag (1,4) truth table iii ? address busy arbitration notes: 1. pins busy l and busy r are both outputs for idt7130 (master). both are inputs for idt7140 (slave). busy x outputs on the idt7130 are open drain, not push-pull outputs. on slaves the busy x input internally inhibits writes. 2. 'l' if the inputs to the opposite port were stable prior to the address and enable inputs of this port. 'h' if the inputs to the opposite port became stable after the address and enable inputs of this port. if t aps is not met, either busy l or busy r = low will result. busy l and busy r outputs can not be low simultaneously. 3. writes to the left port are internally ignored when busy l outputs are driving low regardless of actual logic level on the pin. writes to the right port are internally ignored when busy r outputs are driving low regardless of actual logic level on the pin. notes: 1. a 0l ? a 10l a 0r ? a 10r . 2. if busy = l, data is not written. 3. if busy = l, data may not be valid, see t wdd and t ddd timing. 4. 'h' = v ih , 'l' = v il , 'x' = don?t care, 'z' = high impedance notes : 1. assumes busy l = busy r = v ih 2. if busy l = v il , then no change. 3. if busy r = v il , then no change. 4. 'h' = high,' l' = low,' x' = don?t care inputs (1 ) function r/ w ce oe d 0-7 x h x z port disabled and in power-down mode, i sb2 or i sb4 xhx z ce r = ce l = v ih , powe r-down mo de, i sb1 or i sb3 llxdata in data o n port written into memo ry (2) hlldata out data in memory output on port (3 ) h l h z high impedance outputs 2689 tbl 13 left port right port function r/ w l ce l oe l a 9l -a 0l int l r/ w r ce r oe r a 9r -a 0r int r llx3ffxxxx x l (2) set right int r flag xxx x xxl l 3ff h (3) rese t rig ht int r flag xxx x l (3) l l x 3fe x set left int l flag xll3fe h (2) xxxxxreset left int l flag 2689 tbl 14 inputs outputs function ce l ce r a 0l -a 9l a 0r -a 9r busy l (1) busy r (1 ) x x no match h h normal h x match h h normal x h match h h normal l l match (2) (2) write inhibit (3) 2689 tbl 15
17 idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges functional description the idt7130/idt7140 provides two ports with separate control, address and i/o pins that permit independent access for reads or writes to any location in memory. the idt7130/idt7140 has an automatic power down feature controlled by ce . the ce controls on- chip power down circuitry that permits the respective port to go into a standby mode when not selected ( ce = v ih ). when a port is enabled, access to the entire memory array is permitted. interrupts if the user chooses the interrupt function, a memory location (mail box or message center) is assigned to each port. the left port interrupt flag ( int l ) is asserted when the right port writes to memory location 3fe (hex), where a write is defined as the ce r = r/ w r = v il per truth table ii. the left port clears the interrupt by access address location 3fe access when ce l = oe l = v il, r/w is a "don't care". likewise, the right port interrupt flag ( int r ) is asserted when the left port writes to memory location 3ff (hex) and to clear the interrupt flag ( int r ), the right port must access the memory location 3ff. the message (8 bits) at 3fe or 3ff is user-defined, since it is an addressable sram location. if the interrupt function is not used, address locations 3fe and 3ff are not used as mail boxes, but as part of the random access memory. refer to truth table ii for the interrupt operation. busy logic busy logic provides a hardware indication that both ports of the ram have accessed the same location at the same time. it also allows one of the two accesses to proceed and signals the other side that the ram is ?busy?. the busy pin can then be used to stall the access until the operation on the other side is completed. if a write operation has been attempted from the side that receives a busy indication, the write signal is gated internally to prevent the write from proceeding. the use of busy logic is not required or desirable for all applica- tions. in some cases it may be useful to logically or the busy outputs together and use any busy indication as an interrupt source to flag the event of an illegal or illogical operation. in slave mode the busy pin operates solely as a write inhibit input pin. normal operation can be programmed by tying the busy pins high. if desired, unintended write operations can be prevented to a port by tying the busy pin for that port low. the busy outputs on the idt7130 ram (master) are open drain type outputs and require open drain resistors to operate. if these rams are being expanded in depth, then the busy indication for the resulting array does not require the use of an external and gate. width expansion with busy logic master/slave arrays when expanding an ram array in width while using busy logic, one master part is used to decide which side of the ram array will receive a busy indication, and to output that indication. any number of slaves to be addressed in the same address range as the master, use the busy signal as a write inhibit signal. thus on the idt7130/idt7140 rams the busy pin is an output if the part is master (idt7130), and the busy pin is an input if the part is a slave (idt7140) as shown in figure 3. if two or more master parts were used when expanding in width, a split decision could result with one master indicating busy on one side of the array and another master indicating busy on one other side of the array. this would inhibit the write operations from one port for part of a word and inhibit the write operations from the other port for the other part of the word. the busy arbitration, on a master, is based on the chip enable and address signals only. it ignores whether an access is a read or write. in a master/slave array, both address and chip enable must be valid long enough for a busy flag to be output from the master before the actual write pulse can be initiated with either the r/ w signal or the byte enables. failure to observe this timing can result in a glitched internal write inhibit signal and corrupted data in the slave. figure 3. busy and chip enable routing for both width and depth expansion with idt7130 (master) and idt7140 (slave)rams. 2689 drw 18 master dual port ram busy l busy r ce master dual port ram busy l busy r ce slave dual port ram busy l busy r ce slave dual port ram busy l busy r ce busy l busy r d e c o d e r 5v 5v 270 ? 270 ?
idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges 18 ordering information notes : 1. contact your local sales office for industrial temp range for other speeds, packages and powers. 2. green parts available. for specific speeds, pacakges and powers contact your local sales office. 3. for "p", plastic dip, when ordering green package the suffix is "pdg". 48-pin plastic dip (p48-1) 48-pin sidebraze dip (c48-2) 52-pin plcc (j52-1) 48-pin lcc (l48-1) 48-pin ceramic flatpack (f48-1) 64-pin tqfp (pn64-1) 64-pin stqfp (pp64-1) xxxx idt device type a999 a a power speed package process/ temperature range 7130 7140 speed in nanoseconds 8k (1k x 8-bit) master dual-port ram 8k (1k x 8-bit) slave dual-port ram commercial plcc, tqfp and stqfp only commercial, industrial & military commercial & military commercial, industrial & military commercial, industrial & military 2689 drw 19 blank i (1) b commercial (0 cto+70 c) industrial (-40 cto+85 c) military (-55 c to +125 c) compliant to mil-prf-38535 qml p c j l48 f pf tf 20 25 35 55 100 la sa low power standard power , a ggreen (2) (3) datasheet document history 03/15/99: initiated datasheet document history converted to new format cosmetic and typographical corrections pages 2 and 3 added additional notes to pin configurations 06/08/99: changed drawing format 08/02/99: page 2 corrected package number in note 3 09/29/99: page 2 fixed pin 1 in dip pin configuration 11/10/99: page 1 & 18 replaced idt logo 06/23/00: page 4 increased storage temperature parameters clarified t a parameter page 5 dc electrical parameters?changed wording from "open" to "disabled" page 10 changed 500mv to 0mv in notes 01/08/02: page 1 added ceramic flatpack to 48-pin package offerings page 2 & 3 added date revision to pin configurations page 4, 5, 8, 10 , removed industrial temp option footnote from all tables 12,14 & 15 continued on page 19
19 idt7130sa/la and idt7140sa/la high-speed 1k x 8 dual-port static sram military, industrial and commercial temperature ranges datasheet document history (cont'd) 01/08/02: page 5, 8, 10, 12, & 14 added industrial temp for 25ns to dc & ac electrical characteristics page 5, 8, 10, 12, & 14 removed industrial temp for 35ns to dc & ac electrical characteristics page 18 added industrial temp for 25ns and removed industrial temp for 35ns in ordering information updated industrial temp option footnote page 1 & 19 replaced idt tm logo with idt ? logo 01/11/06: page 1 added green availability to features page 18 added green indicator to ordering information page 1 & 19 replaced old idt tm with new idt tm logo 04/14/06: page 18 added "pdg" footnote to the ordering information the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com

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